Tuesday, February 5, 2013

Memory

From Intel spec

http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/3rd-gen-core-desktop-vol-1-datasheet.pdf


 Data Scrambling

The memory controller incorporates a DDR3 Data Scrambling feature to minimize the
impact of excessive di/dt on the platform DDR3 VRs due to successive 1s and 0s on the
data bus. Past experience has demonstrated that traffic on the data bus is not random.
Rather, it can have energy concentrated at specific spectral harmonics creating high
di/dt that is generally limited by data patterns that excite resonance between the
package inductance and on die capacitances. As a result the memory controller uses a
data scrambling feature to create pseudo-random patterns on the DDR3 data bus to
reduce the impact of any excessive di/dt.

Interleaving or Dual-Channel Symmetric mode,

Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum 
performance on real world applications. Addresses are ping-ponged between the 
channels after each cache line (64-byte boundary). If there are two requests, and the 
second request is to an address on the opposite channel from the first, that request can 
be sent before data from the first request has returned. If two consecutive cache lines 
are requested, both may be retrieved simultaneously, since they are ensured to be on 
opposite channels. Use Dual-Channel Symmetric mode when both Channel A and 
Channel B DIMM connectors are populated in any order, with the total amount of 
memory in each channel being the same.

When both channels are populated with the same memory capacity and the boundary 
between the dual channel zone and the single channel zone is the top of memory, the 
IMC operates completely in Dual-Channel Symmetric mode.

No comments:

Post a Comment